What You’ll Be Doing:
• Hands on Serdes and other Analog IP design and development.
• Analyzing various mixed signal techniques for power reduction, performance enhancement, and area reduction.
• Developing Analog Full custom circuit macros for High Speed PHY IP in advanced technology nodes.
• Collaborating with silicon test and debug experts for Sim2Sil correlation.

Candidate must be MS or senior degree in EE with 6+ years of hands-on experience in mixed signal analog, clock, and data path circuit design.

key qualifications include the following:
• In-depth familiarity with transistor-level circuit design and CMOS design fundamentals.
• Deep knowledge of RF blocks design such as VGA, CTLE, ADC, PLL, CDR, PVT, Bandgap and up/down converters.
• Experience in designing Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits.
• Proficiency in high-speed digital circuit design and timing/phase noise analysis.

The preferred candidate should have followed experience:
• Detailed design experience with various SERDES sub-circuits, including VGA, CTLE, ADC, PLL, CDR and more.
• Experience with custom digital design and optimizing analog/digital interactions.
• Understanding of design for reliability and layout effects, as well as ESD issues.
• Proficiency with tools for schematic entry, physical layout, and design verification.
• Experience of SPICE simulators and simulation methods.